| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a delay circuit by which PVT sensitivity is automatically alleviated. <P>SOLUTION: A delay circuit 100 is provided with a capacitive element consisting of nMOS transistors 141, 142 between an input inverter circuit 110 and an output inverter circuit 120. The input inverter circuit 110 is provided with a pMOS transistor PM1 and an nMOS transistor NM1 which are serially connected between a power supply potential VDD and a ground potential VSS through a resistance R1. There are provided pMOS transistors 151, 152 between a signal line 130 and gates of the nMOS transistors 141, 142. In this configuration, when an input signal changes from L to H, the PVT sensitivity of the delay circuit is automatically alleviated. <P>COPYRIGHT: (C)2011,JPO&INPIT</p> |
