发明名称 |
PHASE LOCK LOOP WITH A MULTIPHASE OSCILLATOR |
摘要 |
<p>A phase lock loop utilizes a multiphase oscillator having a plurality of digital inputs. A plurality of DQ flip-flops, offset in time from each other generate a plurality of control signals to remove control phase information from the oscillator in digital form. A DQ flip-flop connected between any two digital inputs on the oscillator determines direction of the traveling wave. The direction and phase information address a look-up table to determine the current fractional phase of the oscillator. A divide by N circuit is used to reduce the oscillator frequency. A total phase indicator signal for the oscillator is determined using the current fractional phase. The total phase is compared to a reference phase to produce a control signal for making adjustments to the oscillator. In a feed-forward path, frequency dividers divide a high frequency signal to a lower desired frequency, thereby increasing phase resolution.</p> |
申请公布号 |
WO2010138291(A1) |
申请公布日期 |
2010.12.02 |
申请号 |
WO2010US34029 |
申请日期 |
2010.05.07 |
申请人 |
PANASONIC CORPORATION;LIANG, PAUL CHENG-PO;TAKINAMI, KOJI |
发明人 |
LIANG, PAUL CHENG-PO;TAKINAMI, KOJI |
分类号 |
H03L7/099 |
主分类号 |
H03L7/099 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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