| 摘要 |
PROBLEM TO BE SOLVED: To reduce capacitance with an adjacent cell, and to improve a coupling ratio. SOLUTION: This semiconductor storage device includes: a semiconductor substrate 101; a plurality of first insulation films 103 formed on the semiconductor substrate at predetermined intervals; element isolation regions 102 formed along a bit-line direction between the first insulation films; charge storage layers 104 each having a first charge storage film 104a formed on the first insulation film, a second charge storage film 104b formed on the first charge storage film and having a width in a word-line direction smaller than that of the first charge storage film, and a third charge storage film 104c formed on the second charge storage film and having a width in the word-line direction larger than that of the second charge storage film; second insulation films 107 each formed between the second charge storage film and the element isolation region; a third insulation film 105 formed along a second direction on the charge storage layers and the element isolation regions; and a control gate electrode 106 formed on the third insulation film. COPYRIGHT: (C)2011,JPO&INPIT |
