发明名称 SEMICONDUCTOR MEMORY DEVICE, MEMORY CONTROLLER THAT CONTROLS THE SAME, AND INFORMATION PROCESSING SYSTEM
摘要 To include a power-down control circuit that suspends an operation of a predetermined internal circuit in response to a power-down command, and an external terminal to which a selection signal is input from outside simultaneously with issuance of a power-down command. The power-down control circuit suspends an operation of a DLL circuit when the selection signal is at a low level, and continues an operation of the DLL circuit when the selection signal is at a high level. According to the present invention, by using the selection signal input simultaneously with a power-down command, mode selection can be made on-the-fly.
申请公布号 US2010302893(A1) 申请公布日期 2010.12.02
申请号 US20100776964 申请日期 2010.05.10
申请人 ELPIDA MEMORY, INC. 发明人 SATO TAKENORI;FUJISAWA HIROKI
分类号 G11C5/14;G11C7/00 主分类号 G11C5/14
代理机构 代理人
主权项
地址