SEMICONDUCTOR MEMORY DEVICE

摘要

Provided are first and second inverters (20, 30) for memorizing data by mutually connecting the output of the first inverter to the input of the second inverter, and vice versa; a CMOS switch (40) which connects the input of the first inverter (20) to a writing bit line (WBL); a reading MOS transistor (51) the gate of which is connected to the output of the first inverter (20); and a MOS switch (52) which connects the MOS transistor (51) to a reading bit line (RBL). The first and second inverters (20, 30) are of different sizes, and are respectively connected to different source power supplies.