NAND FLASH MEMORY WITH INTEGRATED BIT LINE CAPACITANCE
摘要
<p>Method and apparatus for outputting data from a memory array having a plurality of non-volatile memory cells arranged into rows and columns. In accordance with various embodiments, charge is stored in a volatile memory cell connected to the memory array, and the stored charge is subsequently discharged from the volatile memory cell through a selected column. In some embodiments, the volatile memory cell is a dynamic random access memory (DRAM) cell from a row of said cells with each DRAM cell along the row coupled to a respective column in the memory array, and each column of non-volatile memory cells comprises Flash memory cells connected in a NAND configuration.</p>
申请公布号
WO2010138219(A1)
申请公布日期
2010.12.02
申请号
WO2010US25193
申请日期
2010.02.24
申请人
SEAGATE TECHNOLOGY LLC;JUNG, CHULMIN;LIU, HONGYUE;LEE, BRIAN;LU, YONG;SETIADI, DADI
发明人
JUNG, CHULMIN;LIU, HONGYUE;LEE, BRIAN;LU, YONG;SETIADI, DADI