Periphery barrier structure for integrated circuits

摘要

Chip Outline Band (COB) structure for an integrated circuit integrated in a semiconductor chip having a semiconductor substrate (1) of a first conductivity type and biased at a common reference potential (GND) of the integrated circuit, the COB structure comprising a substantially annular region (3;30) formed in the substrate (1) along a periphery thereof, and at least one annular conductor region (40,60) superimposed on and contacting the substantially annular region (3;30), characterized in that said substantially annular region (3;30) is electrically connected at said common reference potential (GND).