| 摘要 |
A delay circuit (100) includes capacitor elements constituted of nMOS transistors (141, 142) between an input inverter circuit (110) and an output inverter circuit (120). The input inverter circuit (110) includes a pMOS transistor (PM1) and an nMOS transistor (NM1) that are directly connected between a power source potential (VDD) and a ground potential (VSS) through a resistor (R1). Between a signal line (130) and the gate of the nMOS transistor (141), and between the signal line (130) and the gate of the nMOS transistor (142), pMOS transistors (151, 152) are provided, respectively. In this structure, in the case where an input signal is changed from L to H, the PVT sensitivity of a delay circuit is automatically alleviated. As a result, the PVT sensitivity is automatically alleviated.
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