发明名称 PROGRAM, APPARATUS, AND METHOD FOR SUPPORTING VERIFICATION
摘要 PROBLEM TO BE SOLVED: To efficiently perform verification processing of high quality. SOLUTION: In a verification support apparatus, normal simulation by a random test pattern generated in accordance with a set Seed number is executed as in a conventional technology by steps S101-S109. Then, unverified parts are extracted, the processing at steps S110-S119 is used to obtain verification results with respect to the conditions, a simulation result when a condition similar to one to be verified is verified is applied to efficiently obtain a verification result of a desired condition. COPYRIGHT: (C)2011,JPO&INPIT
申请公布号 JP2010267209(A) 申请公布日期 2010.11.25
申请号 JP20090120001 申请日期 2009.05.18
申请人 FUJITSU SEMICONDUCTOR LTD 发明人 TANOWAKI JUN;SUZUKI NORIFUMI;TANAKA HIROYUKI
分类号 G06F17/50;G01R31/3183;H01L21/82 主分类号 G06F17/50
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