发明名称 |
CLOCK CIRCUIT FOR DIGITAL CIRCUIT |
摘要 |
A method of saving power in a digital circuit driven by a clock running at a rate R, comprising reducing said rate R to a lower rate R′ during periods when said digital circuit is operating at a capacity less than its maximum capacity, and wherein the change from rate R to rate R′ is carried out as a smooth transition.
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申请公布号 |
US2010295582(A1) |
申请公布日期 |
2010.11.25 |
申请号 |
US20100780243 |
申请日期 |
2010.05.14 |
申请人 |
ZARLINK SEMICONDUCTOR INC. |
发明人 |
GAULIN LOUISE;ABOU SEIDO MAAMOUN;RODRIGUES SILVANA GONCALA |
分类号 |
H03B19/00 |
主分类号 |
H03B19/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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