发明名称 METHOD FOR FORMING SOLDER RESIST AND CIRCUIT BOARD
摘要 PROBLEM TO BE SOLVED: To provide a method for obtaining a circuit board in which no bonding failure occurs by reducing a bleeding region of a solder resist regardless of the physical property of the solder resist. SOLUTION: In a method for forming a solder resist layer formed by overlapping a first solder resist layer and a second resist layer on metal wiring of a circuit board, the second solder resist layer is formed so that an end of the second solder resist layer is located on a side where the metal wires are exposed rather than an end of the first solder resist layer, while the first solder resist layer bleeds between the metal wiring at the end of the first solder resist layer. COPYRIGHT: (C)2011,JPO&INPIT
申请公布号 JP2010267693(A) 申请公布日期 2010.11.25
申请号 JP20090116254 申请日期 2009.05.13
申请人 TORAY IND INC 发明人 NISHIOKA KAZUYA;OKUYAMA FUTOSHI
分类号 H05K3/28 主分类号 H05K3/28
代理机构 代理人
主权项
地址