发明名称 ARITHMETIC CIRCUIT AND POWER SAVING METHOD
摘要 An arithmetic circuit includes a rearranging unit that rearranges input signals sequentially inputted to the rearranging unit, so that current input signals do not change from immediately previous input signals, and an arithmetic processing unit that performs an arithmetic process on the rearranged input signals rearranged by the rearranging unit.
申请公布号 US2010299382(A1) 申请公布日期 2010.11.25
申请号 US20100783085 申请日期 2010.05.19
申请人 FUJITSU LIMITED 发明人 ABE KAZUHIRO
分类号 G06F17/14 主分类号 G06F17/14
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