| 摘要 |
Techniques for designing a buffer capable of working with low supply voltages, and having active output impedance matching capability to optimize power delivery to a wide range of loads. In an exemplary embodiment, cascode transistors are provided in a buffer architecture employing common-source transistors having unequal width-to-length ratios (W/L) and a resistance having a corresponding fixed ratio to the load. At least one of the cascode transistors may be dynamically biased to minimize a difference between the drain voltages of the common-source transistors. In a further exemplary embodiment, the output impedance of the buffer may be actively tuned by selectively enabling a set of tuning transistors coupled in parallel with the load. Further techniques for providing a calibration mode and an operation mode are described.
|
