| 摘要 |
A memory circuit having a global signal driving circuit, which, when a first read signal is inputted from a first bit signal line with a column signal inputted from a column signal line, outputs the first read signal as a global signal from a global signal line, and, when a first driving write signal is inputted from the first bit signal line, inhibits the first driving write signal from being outputted to the global signal line on the basis of a first write signal inputted from a first write signal line.
|
