| 摘要 |
PROBLEM TO BE SOLVED: To reduce man-hours required for the layout correction of a semiconductor integrated circuit. SOLUTION: The layout verification method includes: a mismatched figure obtaining process (1000) for obtaining a mismatched figure, obtained by comparing laid-out figures in two verification areas, with which the laid-out figures do not coincide with each other; a mismatched figure determining process (1100) for determining in which of the two verification areas the mismatched figure exists; a mismatched distance calculating process (1200) for calculating a mismatched distance serving as a distance between the mismatched figure and an element to be verified, among two elements, in the verification area in which the mismatched figure exists on the basis of the result of the mismatched figure determining process (1100); and a characteristic-influence calculating process (7110) for calculating the influence of the mismatched figure exerted on characteristics of the element to be verified in accordance with the mismatched distance. COPYRIGHT: (C)2011,JPO&INPIT
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