| 摘要 |
A delay apparatus of a semiconductor integrated circuit includes a control signal generating unit configured to generate a block control signal and a unit control signal in response to a delay control signal; a plurality of delay blocks, connected in series to each other, and configured to generate a delay clock signal by delaying an input clock signal, wherein each of the delay blocks includes a predetermined number of unit delayers, and the plurality of the delay blocks are configured to be selectively activated in response to the block control signal; and a minute delay unit including a predetermined number of unit delayers and configured to generate an output clock signal by delaying the delay clock signal by adjusting an activation number of the provided unit delayers in response to the unit control signal.
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