发明名称 |
Method and apparatus for increasing the efficiency of an emulation engine |
摘要 |
A method and apparatus for a memory efficient hardware emulator. The emulator comprises a plurality of processor dusters having data within the duster is stored in at least one data array, where the at least one data array comprises a plurality of sub-arrays. The sub-arrays that are not of uniform size (e.g., the size of each sub-array is determined by the probability that a particular sub-array will be accessed by the processor during a future emulation step). For example, at least one first sub-array is equal in depth to instruction memory within a processor (i.e., equal to the number of instructions in an emulation cycle), and the remaining sub-arrays are a fractional depth of the first sub-array.
|
申请公布号 |
US7827023(B2) |
申请公布日期 |
2010.11.02 |
申请号 |
US20060344766 |
申请日期 |
2006.02.01 |
申请人 |
CADENCE DESIGN SYSTEMS, INC. |
发明人 |
BEAUSOLEIL WILLIAM F.;ELMUFDI BESHARA G.;POPLACK MITCHELL G.;SU TAI |
分类号 |
G06F17/50;G06F9/44;G06F9/45;G06F9/455;G06F13/36;H03K17/693;H03K19/00 |
主分类号 |
G06F17/50 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|