| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a technology for reducing power consumption of an LSI. <P>SOLUTION: A method and an apparatus for distributing a clock signal to a digital circuit include: a step of generating a clock signal; and a step of delaying, advancing or leaving the phase of the clock signal according to a control signal to generate an output clock signal. Wherein, a phase difference to be an amount of delay or advancement between the clock signal and the output clock signal is changed according to timewise variation in magnitude of a power supply voltage of the digital circuit. <P>COPYRIGHT: (C)2011,JPO&INPIT</p> |
