发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
摘要 When a high-voltage output is Hi, a first N-type transistor and a second P-type transistor are in an OFF state, and a second N-type transistor and a first P-type transistor are in an ON state, where a high voltage is applied to drain-source of the first N-type transistor. In a process to shift the high voltage output to Lo, a gate potential of the first N-type transistor is once put to an intermediate state between VDD and GND to lower a drain-source voltage of the first N-type transistor, then the gate potential is raised to VDD. In this manner, a state where the drain-source voltage of the first N-type transistor is large and also a drain current of the same is large is avoided, so that an On withstand voltage of the level shift circuit is increased, thereby preventing a breakdown.
申请公布号 US2010271103(A1) 申请公布日期 2010.10.28
申请号 US20090429172 申请日期 2009.04.23
申请人 HITACHI, LTD. 发明人 MIYAMOTO NAO;AIDA TATSUHIRO;YABUKI SHINOBU
分类号 H03L5/00 主分类号 H03L5/00
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