| 摘要 |
A FIFO buffer circuit is provided which, in data transmission between two circuit areas having different combinations of a power supply voltage and an operation clock frequency, can perform voltage level and clock rate conversion at the same place and time. In an input side area are a plurality of data entry registers, a write entry management circuit and a full signal generating circuit. In an output side area are a read entry management circuit, an empty signal generating circuit and an output selector. On the boundary between the input and output sides are entry management flag circuits that manage the presence or absence of effective data in the respective data entries; and voltage level converting circuits that convert voltage levels of the outputs of the data entry registers to the voltage levels of the output side. In this way, the clock rate replacements and voltage level conversions are performed.
|
