METHOD FOR ARRANGING VOLTAGE SUPPLY PLANES IN A PRINTED CIRCUIT BOARD TO WHICH IS ATTACHED A SEMICONDUCTOR DEVICE FOR REDUCTION OF JITTER AND PCB HAVING SUCH AN ARRANGEMENT

摘要

A model and method are provided for lowering device jitter by controlling the stackup of PCB planes so as to minimize inductance between a FPGA and PCB voltage planes for critical core voltages within the FPGA. Furthermore, a model and method are provided for lowering jitter by controlling the stackup of package substrate planes so as to minimize inductance between a die and substrate voltage planes for critical core voltages within the die.