发明名称 |
Pipelined clock stretching circuitry and method for I2C logic system |
摘要 |
A system for increasing the data throughput of an I2C bus including a serial clock conductor (3) for conducting a serial clock signal (SCK) and a serial data conductor (2) for conducting a serial data signal (SDA) includes clock-stretching control circuitry (15) coupled to the serial clock conductor (3) for stretching the serial clock signal (SCK) by holding the serial clock conductor (3) at a predetermined level to cause a master device (10) to stop sending the serial clock signal, and circuitry (FIG. 3) in the slave device (5) for releasing stretching of the serial clock signal (SCK) in response to a determination by the slave device (5) that stretching of the serial clock signal (SCK) is unnecessary.
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申请公布号 |
US7818604(B2) |
申请公布日期 |
2010.10.19 |
申请号 |
US20080040051 |
申请日期 |
2008.02.29 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
SARIPALLI RAMESH;CHEUNG HUGO;GOAS BENOIT |
分类号 |
G06F1/04;G06F1/12;G06F5/06;G06F13/42 |
主分类号 |
G06F1/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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