发明名称 Method of manufacturing electronic component package
摘要 In a method of manufacturing an electronic component package, first, a plurality of sets of external connecting terminals corresponding to a plurality of electronic component packages are formed by plating on a top surface of a substrate to thereby fabricate a wafer. The wafer includes a plurality of pre-base portions that will be separated from one another later to become bases of the respective electronic component packages. Next, at least one electronic component chip is bonded to each of the pre-base portions of the wafer. Next, electrodes of the electronic component chip are connected to the external connecting terminals. Next, the electronic component chip is sealed. Next, the wafer is cut so that the pre-base portions are separated from one another and the plurality of bases are thereby formed.
申请公布号 US7816176(B2) 申请公布日期 2010.10.19
申请号 US20070806047 申请日期 2007.05.29
申请人 HEADWAY TECHNOLOGIES, INC.;SAE MAGNETICS (H.K.) LTD. 发明人 SASAKI YOSHITAKA;SHIMIZU TATSUSHI
分类号 H01L21/00;H05K1/02 主分类号 H01L21/00
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