| 摘要 |
A method, algorithm, architecture, circuits, and/or systems for using a delay-locked loop (DLL) for phase adjustment in a direct conversion radio receiver are disclosed. In one embodiment, a receiver circuit can include: (i) a voltage-controlled oscillator (VCO) for providing a reference clock; (ii) a delay element that can receive the reference clock and provide a delay adjustment signal; (iii) a first channel for receiving a radio signal and providing a recovered radio signal from the radio signal and the delay adjustment signal, where the first channel includes a first mixer and a first filter; and (iv) a second channel for receiving the radio signal and a phase adjustment signal derived from the delay adjustment signal and for providing a delay control signal to the delay element from the radio signal and the phase adjustment signal, where the second channel includes a second mixer and a second filter.
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