发明名称 Semiconductor integrated circuit device preventing logic transition during a failed clock period
摘要 A semiconductor integrated circuit device is disclosed. The semiconductor integrated circuit device includes a first circuit whose output never or seldom changes when the output from an Enable generator is off, a second circuit whose output frequently changes, an input controller which receives the respective outputs from the second circuit and the Enable generator and passes through the input from the second circuit only when the output from the Enable generator is on, a combination circuit which receives the respective outputs from the first circuit and the input controller, and a memory which receives the output from the combination circuit and is driven by the output from the clock controller.
申请公布号 US7818602(B2) 申请公布日期 2010.10.19
申请号 US20070684727 申请日期 2007.03.12
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 KAJIHARA HIROTSUGU
分类号 G06F1/00 主分类号 G06F1/00
代理机构 代理人
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