| 摘要 |
A high efficiency PLD architecture having adjacent logic elements that can be selectively combined to perform higher order logic functions than can be performed alone by a single logic element. The programmable logic device includes a logic block having a first logic element including a first look up table. The first look up table includes a first pair of sub-function generators and is capable of implementing logic functions of a first order. The logic block also includes a second logic element having a second input look up table including a second pair of sub-function generators. Programmable sharing circuitry is also included in the logic block. The programmable sharing circuitry selectively couples the first pair of sub-function generators and the second pair of sub-function generators so that the first logic element is capable of performing logic functions of either (i) the first order, or (ii) a second order, wherein the second order is higher than the first order.
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