发明名称 |
Systems and methods for improved bit loading for discrete multi-tone modulated multiple latency applications |
摘要 |
Systems and methods for performing bit loading in a dual latency data transmission system. In a computer network, such as an XDSL-based network, carrier channels are allocated between two latency paths. Error sensitive information is transmitted over a latency path employing one or more forward error correction techniques. Latency sensitive information that is relatively more tolerant of errors is transmitted over the other latency path. Rather than employing the lowest coding gain for carrier channels having the two different latency paths, the highest coding gain for each path is used by applying different target S-N-R margins for carrier channels having different latency paths.
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申请公布号 |
US7813434(B2) |
申请公布日期 |
2010.10.12 |
申请号 |
US20060559772 |
申请日期 |
2006.11.14 |
申请人 |
IKANOS COMMUNICATIONS, INC. |
发明人 |
WU YAN;CAI LUJING;SCHOLTZ WILLIAM;LANGBERG EHUD |
分类号 |
H04K1/10;H04L27/28 |
主分类号 |
H04K1/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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