发明名称 INTEGRATED CIRCUIT, DEBUGGING CIRCUIT AND DEBUGGING COMMAND CONTROL METHOD
摘要 <P>PROBLEM TO BE SOLVED: To provide an integrated circuit for controlling a bus right acquisition request and approval such that a bus can be efficiently used, when an internal resource such as a memory can be directly accessed from a built-in debugging circuit. <P>SOLUTION: The integrated circuit includes: a bus; a processing unit executing a user program; and the debugging circuit transferring an instruction inside an instruction register to the processing unit via the bus in response to an instruction transfer request from the processing unit, connected to the bus. When the processing unit suspends the execution of the user program and performs the instruction transfer request to the debugging circuit, the debugging circuit performs a response for freeing a use right of the bus from the processing unit in a period between the instruction transfer request and instruction transfer operation. <P>COPYRIGHT: (C)2011,JPO&INPIT
申请公布号 JP2010225094(A) 申请公布日期 2010.10.07
申请号 JP20090074359 申请日期 2009.03.25
申请人 FUJITSU SEMICONDUCTOR LTD 发明人 SATO SHUHEI;SATO TAKASHI
分类号 G06F11/28 主分类号 G06F11/28
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