发明名称 MULTIPLEXER
摘要 <p><P>PROBLEM TO BE SOLVED: To assure stable operation by suppressing rough changes in amplitude of a clock signal by multiplex reflections. <P>SOLUTION: Multiplex reflection of the clock signal is suppressed by connecting a capacitor 27a having a capacitance value C which is almost two times the input capacitance C<SB>L</SB>of each latch circuit and satisfying the relation of the characteristic impedance (Z)=√(L/C), where the inductance of the length equal to half the line conductor is defined as L, between the intermediate part of the line conductor of the second transmission line 27 and the earth and between the intermediate part of the line conductor of a third transmission line 28 and the ground among a first to fourth transmission lines 26 to 29, forming a clock supplying circuit 25 for supplying clock signal to each latch circuit of a first and second shift circuits 11 and 12; and by also terminating, the fourth transmission line 29 with a resistance R equal to the characteristic impedance. <P>COPYRIGHT: (C)2011,JPO&INPIT</p>
申请公布号 JP2010226626(A) 申请公布日期 2010.10.07
申请号 JP20090073891 申请日期 2009.03.25
申请人 ANRITSU CORP 发明人 ARAYASHIKI YUTAKA
分类号 H03K5/00;G06F1/04;G06F3/00 主分类号 H03K5/00
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