发明名称 SEMICONDUCTOR DEVICE CONFIGURATION METHOD
摘要 A plurality of three-terminal variable resistance switching elements each having a source electrode, a drain electrode, and a gate electrode are connected to each other in series. The source electrode of each of the three-terminal variable resistance switching elements and the drain electrode of its adjacent three-terminal variable resistance switching element are connected to each other through a wiring segment to form a lane. A potential holding section for holding a predetermined potential level is connected to the wiring segment. A column group is configured by selecting one of the three-terminal variable resistance elements in each lane. A common gate line is connected to each of the gate electrodes of the three-terminal variable resistance elements belonging to the column group.
申请公布号 US2010246240(A1) 申请公布日期 2010.09.30
申请号 US20080742018 申请日期 2008.09.09
申请人 NAKAYA SHOGO 发明人 NAKAYA SHOGO
分类号 G11C11/00 主分类号 G11C11/00
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