发明名称 |
WAFER LEVEL, CHIP SCALE SEMICONDUCTOR DEVICE PACKAGING COMPOSITION, AND METHOD RELATING THERETO |
摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide wafer level, chip scale semiconductor device packaging compositions capable of providing high density, small scale circuitry lines without the use of photolithography, and a method relating thereto. <P>SOLUTION: The wafer level package comprises a stress buffer layer 105 containing a polymer binder and a spinel crystal filler in both a non-activated and a laser activated form. The stress buffer layer 105 is patterned with a laser to thereby activate the filler, and the laser ablation path can then be selectively metalized. <P>COPYRIGHT: (C)2010,JPO&INPIT</p> |
申请公布号 |
JP2010212665(A) |
申请公布日期 |
2010.09.24 |
申请号 |
JP20100020332 |
申请日期 |
2010.02.01 |
申请人 |
E I DU PONT DE NEMOURS &, CO |
发明人 |
LEE YUEH-LING;TSAI BIN-HONG COLIN;CHU JAMES;CHEN CHENG-CHUNG;YUN HAO |
分类号 |
H01L23/12 |
主分类号 |
H01L23/12 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|