| 摘要 |
A format of an inputted video signal is estimated to be based on the total number of vertical lines, and a frequency dividing ratio of a PLL unit is provisionally set at a predetermined value corresponding to the estimated format. Next, the frequency dividing ratio is calculated so that a measured value of a horizontal display width that is measured by a video detecting unit matches a capture width which is the horizontal display width capturable by a frame memory, and the calculated frequency dividing ratio is converted to a multiple of 4. A phase adjustment of the regenerative dot clock is performed against the video signal based on the converted frequency dividing ratio by using the regenerative dot clock generated by the PLL unit. Furthermore, the frequency dividing ratio is recalculated so that the measured value of the horizontal display width that is measured by the video detecting unit matches the capture width by using the regenerative dot clock after finishing the phase adjustment, and the calculated frequency dividing ratio is reset to the PLL unit.
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