Neural network circuit comprising nanoscale synapses and CMOS neurons

摘要

The invention relates to a neural network circuit comprising nanoscale devices (411-415, 421-425) acting as synapses and CMOS circuits (201, 202) acting as neurons. It finds a particular interest for computing circuits and systems involving complex functions or handling of huge amounts of data. Comparing with the existing proposals, this architecture promises small die area, high speed thanks to massively parallel learning and low power. The nanoscale devices (411-415, 421-425) comprise two terminals and are connected to row conductors (221, 222) and to column conductors (231-235) in a matrix-like fashion. A CMOS circuit (201, 202) is connected at one end of each row conductor (221, 222). An electrical characteristic between the two terminals of each nanoscale device (411-415, 421-425) is able to be modified by a signal applied to the second terminal. The neural network further comprises, for each row conductor (221, 222), means (401, 402) for preventing the electrical characteristics of the nanoscale devices (411-415, 421-425) connected to the considered row conductor (221, 222) from being modified by a signal applied to the second terminal of said nanoscale devices.