发明名称 Flat placement of cells on non-integer multiple height rows in a digital integrated circuit layout
摘要 The various embodiments of the present invention generally relate to systems, methods, and computer program products for placement of at least one cell in a digital integrated circuit layout. A global placement grid of coordinates is formed, where the coordinates represent horizontal and vertical directions. A local placement grid of coordinates is also formed for at least one local region, where the local placement grid of coordinates represent horizontal and vertical directions, and where the at least one local region is adapted to support non-integer multiple height rows. At least one cell is associated with the at least one local region formed, and the cell can be placed in the local placement grid of the local region.
申请公布号 US7802219(B2) 申请公布日期 2010.09.21
申请号 US20060565476 申请日期 2006.11.30
申请人 CADENCE DESIGN SYSTEMS, INC. 发明人 TOMAR ANURAG;NOICE DAVE
分类号 G06F17/50 主分类号 G06F17/50
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