发明名称 |
Data processing apparatus and method using FIFO device |
摘要 |
In a data processing apparatus and method using a first-in first-out (FIFO), the data processing apparatus includes a first sampling circuit, a delay circuit, and a FIFO device. The first sampling circuit samples a logic state of input data in response to a first edge of a first clock signal and holds a result of the sampling. The delay circuit receives and delays the first clock signal by a predetermined delay time and outputs a second clock signal. The FIFO device processes the result of the sampling output from the first sampling circuit using a FIFO method in response to a first edge of the second clock signal output from the delay circuit.
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申请公布号 |
US7802123(B2) |
申请公布日期 |
2010.09.21 |
申请号 |
US20070811726 |
申请日期 |
2007.06.12 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
CHAE KWAN-YEOB |
分类号 |
G06F1/12;G06F1/14;G06F13/42 |
主分类号 |
G06F1/12 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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