| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a parallel signal processing processor capable of suppressing reduction in use efficiency of processor elements and capable of achieving the parallel degree of processor elements corresponding to a use state. Ž<P>SOLUTION: SIMD program control parts 2-1, 2-2 output instruction control signals 21-1, 21-2 expressing instructions to be executed by respective processor elements (PEs) 4-1 to 4-12 respectively according to tasks to be executed. Instruction control signal matrix buses 3-1, 3-2 selectively switch the instruction control signals 21-1, 21-2 to the PEs 4-1 to 4-12 according to instruction control signal matrix switching signals 12. A total program control part 1 outputs an instruction control signal matrix switching signal 12 on the basis of the allocation number of processor elements corresponding to tasks to be executed by the SIMD program control parts 2-1, 2-2. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
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