发明名称 Reduced clash GRA interleavers
摘要 Methods, apparatuses, and systems are presented for performing data encoding involving receiving a sequence of data bits, encoding the sequence of data bit according to a code characterized by a parity check matrix (H matrix) to generate a sequence of encoded bits, wherein the H matrix is capable of being expressed as H=[Hp|Hd]=[S|J*P*T], S being a dual-diagonal matrix, J being a single parity check matrix, P being an interleaver permutation matrix, and T being a repeat block matrix, wherein the H matrix is a column permuted version of an original H matrix, wherein clashes associated with an interleaver corresponding to the P matrix are reduced by adopting the H matrix instead of the original H matrix, and outputting the sequence of encoded bits.
申请公布号 US7793190(B1) 申请公布日期 2010.09.07
申请号 US20060463857 申请日期 2006.08.10
申请人 TRELLISWARE TECHNOLOGIES, INC. 发明人 GRAY PAUL KINGSLEY;CHUGG KEITH MICHAEL
分类号 H03M13/00 主分类号 H03M13/00
代理机构 代理人
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