发明名称 Clock distribution techniques for channels
摘要 A circuit includes a first area, a second area, and a third area. The second area includes a locked loop circuit that generates a clock signal. The locked loop circuit receives a supply voltage that is isolated from noise generated in the first area. The third area includes multiple quads of channels and a clock line coupled to route at least one clock signal generated in the second area to the channels in each of the quads. The third area is separate from the second area in the circuit.
申请公布号 US7791370(B1) 申请公布日期 2010.09.07
申请号 US20090470455 申请日期 2009.05.21
申请人 ALTERA CORPORATION 发明人 HOANG TIM TRI;TRAN THUNGOC M.;WONG WILSON;SHUMARAYEV SERGEY
分类号 G06F7/38;H03K19/173 主分类号 G06F7/38
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