发明名称 |
SEMICONDUCTOR DEVICE, METHOD AND DEVICE FOR DESIGNING SEMICONDUCTOR DEVICE, AND FAULT DETECTION METHOD |
摘要 |
<p>A bridge fault occurring between sets of clock signal wiring of a semiconductor device can be easily detected. The semiconductor device provided with a plurality of holding circuits and configured in such a manner that a scan test can be performed, comprises first clock signal wiring and second clock signal wiring to which normal operation clock signals, at least either the frequencies or the phases of which are different from one another, are supplied during the normal operation, and a test clock signal control circuit which, during a test, switches between a state in which a first test clock signal which is the same as that supplied to the first clock signal wiring is supplied to the second clock signal wiring, and a state in which a second test clock signal generated by inverting the first test clock signal or shifting the phase thereof is supplied thereto.</p> |
申请公布号 |
WO2010097851(A1) |
申请公布日期 |
2010.09.02 |
申请号 |
WO2009JP04860 |
申请日期 |
2009.09.25 |
申请人 |
PANASONIC CORPORATION;FUJII, NAOHIRO;DAIO, KINYA;YOSHIMURA, SHINICHI |
发明人 |
FUJII, NAOHIRO;DAIO, KINYA;YOSHIMURA, SHINICHI |
分类号 |
G01R31/28;G06F17/50;H01L21/82;H01L21/822;H01L27/04 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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