发明名称 Semiconductor memory device capable of realizing a chip with high operation reliability and high yield
摘要 A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having a plurality of memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.
申请公布号 US7787277(B2) 申请公布日期 2010.08.31
申请号 US20080052882 申请日期 2008.03.21
申请人 发明人 NAKAMURA HIROSHI;TAKEUCHI KEN;OODAIRA HIDEKO;IMAMIYA KENICHI;NARITA KAZUHITO;SHIMIZU KAZUHIRO;ARITOME SEIICHI
分类号 G11C11/34;G11C16/04;H01L21/8247;H01L27/10;H01L27/105;H01L27/115;H01L29/788;H01L29/792 主分类号 G11C11/34
代理机构 代理人
主权项
地址