发明名称 |
CACHE MEMORY |
摘要 |
PURPOSE: By sanctioning the enforcement voltage signal when accessing the word line having the cache memory is the access time failure the access time delay of the word line is reduced and the access failure of the cache memory can be minimized. CONSTITUTION: It decodes the inputted address signal and the row decoder(10) outputs. Whether the cell having the word line voltage control logic(50) is the access time failure in the word line is included or not the basis voltage signal is outputted according to whether or not. The split wordline driver is connected to the output lines of the row decoder one-to-one. The split wordline driver(20) supplies the basis voltage signal or the enforcement voltage signal outputted from the word line voltage control logic to word lines.
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申请公布号 |
KR20100093915(A) |
申请公布日期 |
2010.08.26 |
申请号 |
KR20090013067 |
申请日期 |
2009.02.17 |
申请人 |
KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION |
发明人 |
CHUNG, SUNG WOO;KONG, JOON HO |
分类号 |
G11C11/41;G11C8/08;G11C8/10 |
主分类号 |
G11C11/41 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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