发明名称 |
Electrical parameter extraction for integrated circuit design |
摘要 |
A system, method, and computer readable medium for generating a parameterized and characterized pattern library for use in extracting parasitics from an integrated circuit design is provided. In an embodiment, a layout of an interconnect pattern is provided. A process simulation may be performed on the interconnect pattern. In a further embodiment, the interconnect pattern is dissected into a plurality of segments taking into account OPC rules. A parasitic resistance and/or parasitic capacitance associated with the interconnect pattern may be determined by a physical model and/or field solver.
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申请公布号 |
US7783999(B2) |
申请公布日期 |
2010.08.24 |
申请号 |
US20080016661 |
申请日期 |
2008.01.18 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
OU TSONG-HUA;CHENG YING-CHOU;LIN CHIA-CHI;LIU RU-GUN;LAI CHIH-MING;WU MIN-HONG;DOONG YIH-YUH;HOU CLIFF;KU YAO-CHING |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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