发明名称 Word line decoder circuit
摘要 A word line decoder circuit is provided in the present invention. The word line decoder circuit comprises at least one local pre-decoder, at least one 3-transistors row driver, a controllable power supply, and a controllable pull-down circuit. The controllable power supply is controlled by an inversed sector select signal to provide a first voltage to the row driver and local pre-decoder. The local pre-decoder uses 5-transistors architecture, in which there are 2 PMOS transistors and 3 NOS transistors. The controllable pull-down circuit pulls down the local pre-decoder and is controlled by a sector select signal and pre-decoding signal. The local pre-decoder receives a local pre-decoding signal to select the row driver. When the row driver is selected, the row driver determines a word line according to a row driver pull-down signal and a row driver pull-up signal.
申请公布号 US7782705(B2) 申请公布日期 2010.08.24
申请号 US20080336547 申请日期 2008.12.17
申请人 ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. 发明人 CHAN JEN-CHIN
分类号 G11C8/00 主分类号 G11C8/00
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