| 摘要 |
A device including a voltage regulator with an adaptive switching frequency circuit for noise-sensitive analog circuits, such as oscillatory systems with phase-lock loops (PLLs) and voltage-controlled oscillators (VCOs) is described. In an exemplary embodiment, the device includes a reference clock oscillator (30, a low-jitter oscillator (170a), a power supply (120, 130a, 140a, 150) including a clock signal input to regulate a power supply voltage (WD-REG) for the low-jitter oscillator, a clock detector to generate a clock detector control signal (BOOST-CLK-SEL) when the low- jitter oscillator output frequency is stable, and a multiplexer (110) to select between a reference clock oscillator output signal (REF-CLK) and a low- jitter oscillator output signal (VCO-CLK) as the clock signal (CLK) input to the power supply to mitigate effects of period jitter in the low- jitter oscillator output signal when the clock detector control signal is asserted. In a further exemplary embodiment, a clock detector control signal is configured to control the multiplexer to select the low- jitter oscillator output signal as the clock signal input to the power supply when the low-jitter oscillator output frequency is stable. |
