发明名称 |
CIRCUITS AND METHODS FOR DFE WITH REDUCED AREA AND POWER CONSUMPTION |
摘要 |
A 1/n-rate decision feedback equalizer (DFE) and method include a plurality of branches. Each branch includes a summer circuit configured to add a feedback signal to a received input, and a latch configured to receive an output of the summer circuit in accordance with a clock signal. A feedback circuit includes a multiplexer configured to receive as input, an output of each branch, the multiplexer having a clocked select input and configured to multiplex the output of each branch to assemble a full rate bit sequence, and a filter configured to provide cancellation of intersymbol interference (ISI) from the received input to be provided to the summer circuit of each branch.
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申请公布号 |
US2010202506(A1) |
申请公布日期 |
2010.08.12 |
申请号 |
US20090366843 |
申请日期 |
2009.02.06 |
申请人 |
BULZACCHELLI JOHN F;KIM BYUNGSUB |
发明人 |
BULZACCHELLI JOHN F.;KIM BYUNGSUB |
分类号 |
H04L27/01;H03K3/00;H03K5/153 |
主分类号 |
H04L27/01 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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