NONVOLATILE SEMICONDUCTOR MEMORY

摘要

When write is performed simultaneously into a plurality of nonvolatile memory cells in a memory cell array (100), the bit lines of the nonvolatile memory cells are connected to M (M is an integer not smaller than 2) data lines (DIO1 to DIOm) by a column address signal.  N (N is an integer not smaller than 1) switches (SW1 to SWn) and a switch control circuit (103) for controlling the N switches are arranged for each of the data lines.  M switch control circuits control M × N switches so as to change the voltage level of the drain voltage applied to the memory cell bit lines or the period of the drain voltage application for each of the memory cells.