| 摘要 |
<p>A processor includes a device (205) providing a throttling power output signal. The throttling power output signal is used to determine when to logically throttle the power consumed by the processor. At least one core (110-i) in the processor includes a pipeline (210) having a decode pipe (213); and a logical power throttling unit (203) coupled to the device to receive the output signal, and coupled to the decode pipe. Following logical power throttling unit (203) receiving the power throttling output signal satisfying a predetermined criterion, the logical power throttling (203) unit causes the decode pipe (213) to reduce an average number of instructions decoded per processor cycle without physically changing the processor cycle or any processor supply voltages.</p> |
