| 摘要 |
A semiconductor device including a clock signal generation circuit and a plurality of circuit blocks operating in synchronization with the clock signal, in which each of the plurality of the circuit blocks conducts resetting treatment receiving the interruption signal reset_in outputted in synchronization with the clock signal in the course of frequency acquisition, whereby the timing margin is improved greatly to facilitate the design of timing for a case of conducting interruption between a plurality of circuit blocks operating at high speed simultaneously and decrease circuit scale and power consumption. |
