SEMICONDUCTOR INTEGRATED CIRCUIT

摘要

PROBLEM TO BE SOLVED: To improve data reading speed in a dual port SRAM performing reading and writing at the same time. SOLUTION: Each memory cell includes: first and second inverters holding data in first and second store nodes; a writing/reading port constructed of first and second N-channel transistors individually connected between a first bit line pair and the first and second store nodes; a first P-channel transistor receiving the data of the first store node to a gate; a second P-channel transistor connected between one of a second bit line pair and the drain of the first P-channel transistor; a third P-channel transistor receiving the data of the second store node to the gate; and a reading port constructed of a fourth P-channel transistor connected between the other of the second bit line pair and the drain of the third P-channel transistor. COPYRIGHT: (C)2010,JPO&INPIT