Apparatus and/or method for variable data rate conversion

摘要

An apparatus generally comprising a first circuit, a second circuit and a third circuit is shown. The first circuit may be configured to generate a phase signal by dividing each cycle of an output clock into a plurality of phase values. The second circuit may be configured to generate an intermediate data signal by interpolating an input data signal sampled with an input clock in response to the phase signal and the output clock. The third circuit configured to generate an output data signal by sampling the intermediate data signal with the output clock.